1. Field of the Invention
The present invention relates to a multiplier, and more specifically to an analog multiplier for multiplying two analog input signals.
2. Description of Related Art
In the prior art, one typical analog multiplier using a Gilbert's circuit as shown in FIG. 1 has been known.
In the circuit shown in FIG. 1, a first differential circuit is composed of a pair of transistors M.sub.21 and M.sub.22 having their sources connected to each other, and a second differential circuit is composed of a pair of transistors M.sub.23 and M.sub.24 having their sources connected to each other. Drains of the transistors M.sub.21 and M.sub.23 are connected to each other, and drains of the transistors M.sub.22 and M.sub.24 are connected to each other. In addition, gates of the transistors M.sub.21 and M.sub.24 are connected to each other, and gates of the transistors M.sub.22 and M.sub.23 are connected to each other. A first input signal V.sub.1 is applied between the gates of the transistors M.sub.21 and M.sub.24 and the gates of the transistors M.sub.22 and M.sub.23, so that the input signal is applied to the first differential circuit in a non-inverted polarity and to the second differential circuit in an inverted polarity.
The common-connected sources of the transistors M.sub.21 and M.sub.22 are connected to a drain of a transistor M.sub.25, and the common-connected sources of the transistors M.sub.23 and M.sub.24 are connected to a drain of a transistor M.sub.26. Sources of the transistors M.sub.25 and M.sub.26 are connected to each other, so that a third differential circuit is formed. The common-connected sources of the transistors M.sub.25 and M.sub.26 are connected through a constant current source 21 to ground. A second input signal V.sub.2 is applied between the gate of the transistor M.sub.25 and the gate of the transistor M.sub.26.
Now, operation of the multiplier as mentioned above will be described.
First, assume that gate widths of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 are W.sub.21, W.sub.22, W.sub.23, W.sub.24, W.sub.25 and W.sub.26, respectively, and gate lengths of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 are L.sub.21, L.sub.22, L.sub.23, L.sub.24, L.sub.25 and L.sub.26, respectively. The gate widths and the gates lengths of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 are set as follows: ##EQU1##
In addition, by expressing a mobility of the transistors by .mu..sub.n and a thickness of a gate capacitance per unit area by Cox, factors .alpha..sub.1 and .alpha..sub.2 are defined as follows: ##EQU2##
Furthermore, assume that a threshold voltage of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 is V.sub.t, and gate-to-source voltages of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 are V.sub.gs21, V.sub.gs22, V.sub.gs23, V.sub.gs24, V.sub.gs25 and V.sub.gs26, respectively. Under these conditions, drain currents I.sub.d21, I.sub.d22, I.sub.d23, I.sub.d24, I.sub.25 and I.sub.d26 of the transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24, M.sub.25 and M.sub.26 are expressed as follows: EQU I.sub.d21 =.alpha..sub.1 (V.sub.gs21 -V.sub.t).sup.2 ( 5) EQU I.sub.d22 =.alpha..sub.1 (V.sub.gs22 -V.sub.t).sup.2 ( 6) EQU I.sub.d23 =.alpha..sub.1 (V.sub.gs23 -V.sub.t).sup.2 ( 7) EQU I.sub.d24 =.alpha..sub.1 (V.sub.gs24 -V.sub.t).sup.2 ( 8) EQU I.sub.d25 =.alpha..sub.1 (V.sub.gs25 -V.sub.t).sup.2 ( 9) EQU I.sub.d26 =.alpha..sub.1 (V.sub.gs26 -V.sub.t).sup.2 ( 10)
Here, the drain currents I.sub.d21, I.sub.d22, I.sub.d23, I.sub.d24, I.sub.d25 and I.sub.d26 and the gate-to-source voltages V.sub.gs21, V.sub.gs22, V.sub.gs23, V.sub.gs24, V.sub.gs25 and V.sub.gs26 have the relation expressed by the following equations: EQU I.sub.d21 +I.sub.d22 =I.sub.d25 ( 11) EQU I.sub.d23 +I.sub.d24 =I.sub.d26 ( 12) EQU I.sub.d25 +I.sub.d26 =I.sub.0 ( 13) EQU V.sub.gs21 -V.sub.gs22 =V.sub.gs24 -V.sub.gs23 =V.sub.1 ( 14) EQU V.sub.gs25 -V.sub.gs26 =V.sub.2 ( 15)
Thus, the following equation (16) can be derived: ##EQU3##
Here, assuming I.sub.d25 -I.sub.d26 =I.sub.V2, the following equations (17) and (18) can be derived from the equations (13) and (16): ##EQU4##
On the other hand, I.sub.V1 is defined by the following equation (19): ##EQU5##
This equation (19) can be modified as follows: ##EQU6##
Thus, the following equation (21) can be derived: ##EQU7##
This equation (21) can be simplified as follows:
First, functions f(x), g(x) and h(x) of "x" can be defined as follows: ##EQU8##
The equation (24) can be developed into the form of a series: ##EQU9##
Here, f'(0), f"(0), . . . and g'(0), g"(0), . . . can be respectively obtained as follows: ##EQU10##
In addition, since EQU f(0)=g(0)=1, h(0)=0 (30)
As a result, the equation (25) can be expressed as follows: EQU h(x)=ax+ . . . (31)
Accordingly, similarly to the above, the equation (21) can be expressed as the following equation (32): ##EQU11##
On the other hand, by referring to the equations (19) and (20), the equation (32) can be modified as the following equation (33): ##EQU12##
Here, if the second and succeeding items (not shown) in the equation (33) are ignored, and if it is assumed that since V.sub.1 is very small, V.sub.1.sup.2 .apprxeq.0, the equation (33) can be simplified as follows: ##EQU13##
Here, I.sub.V1 corresponds to a differential output current (transfer curve) of the differential amplifier driven with a half (Io/2) of the constant current Io so as to respond to the input voltage V.sub.1, and I.sub.V2 corresponds to a differential output current (transfer curve) of the differential amplifier driven with a half (Io/2) of the constant current Io so as to respond to the input voltage V.sub.2. The transfer curve of the differential amplifier can be regarded to be linear if the input voltage is small. Therefore, a multiplication characteristics can be obtained from the equation (34) in a range in which the input voltages V.sub.1 and V.sub.2 are small.
In addition, it will be apparent from the equation (33) that a voltage range allowing the multiplier to have a good linearity is narrower in the input voltage V.sub.1 than in input voltage V.sub.2. Furthermore, if the multiplier is composed of transistors having the same size, the operating ranges of the two input voltages V.sub.1 and V.sub.2 have a relation of ##EQU14##
If the equation (33) is further developed in the form of a series, the following can be obtained: ##EQU15##
Here, if all of items including a second-order and higher orders of the input voltages V.sub.1 and V.sub.2 are neglected, the equation (35) can be expressed as the following equation (36): ##EQU16##
Therefore, this multiplier can give the result of multiplication of the input voltages V.sub.1 and V.sub.2 in the form of I.sub.1 -I.sub.2.
Referring to FIG. 2, there is shown a circuit diagram of another conventional multiplier, which was disclosed in "A Four-Quadrant MOS Analog Multiplier", Jesus Pena-Finol et al, 1987, IEEE International Solid-State cct, Conf. THPM17.4.
A first input voltage V.sub.1 is applied between gates of input transistors M.sub.31 and M.sub.32 having their sources connected to each other, and the common-connected sources of the transistors M.sub.31 and M.sub.32 are connected to a low voltage V.sub.SS through a transistor M.sub.55 acting as a constant current source. Drains of the transistors M.sub.31 and M.sub.32 are connected to a high voltage V.sub.DD through transistors M.sub.35 and M.sub.36, respectively.
A second input voltage V.sub.2 is applied between gates of input transistors M.sub.33 and M.sub.34 having their sources connected to each other, and the common-connected sources of the transistors M.sub.33 and M.sub.34 are connected to the low voltage V.sub.SS through a transistor M.sub.54 acting as a constant current source. Drains of the transistors M.sub.33 and M.sub.34 are connected to the high voltage V.sub.DD through transistors M.sub.37 and M.sub.38, respectively. A gate of the transistor M.sub.37 is connected to a drain of the transistor M.sub.37 itself and a gate of the transistor M.sub.38 is connected to a drain of the transistor M.sub.38 itself. Sources of the transistors M.sub.37 and M.sub.38 are connected to gates of the transistors M.sub.35 and M.sub.36, respectively. The above mentioned transistors constitute a first differential input summing circuit.
Furthermore, the first input voltage V.sub.1 is also applied between gates of input transistors M.sub.41 and M.sub.42 having their sources connected to each other, and the common-connected sources of the transistors M.sub.41 and M.sub.42 are connected to the low voltage V.sub.SS through a transistor M.sub.51 acting as a constant current source. Drains of the transistors M.sub.41 and M.sub.42 are connected to the high voltage V.sub.DD through transistors M.sub.45 and M.sub.46, respectively. In addition, there is provided a pair of transistors M.sub.43 and M.sub.44 having their sources connected to each other. The common-connected sources of the transistors M.sub.43 and M.sub.44 are connected to the low voltage V.sub.SS through a transistor M.sub.52 acting as a constant current source. Drains of the transistors M.sub.43 and M.sub.44 are connected to the high voltage V.sub.DD, respectively, through transistors M.sub.47 and M.sub.48 connected in the form of a load in such a manner that a gate of the transistor M.sub.47 is connected to a drain of the transistor M.sub.47 itself and a gate of the transistor M.sub.48 is connected to a drain of the transistor M.sub.48 itself. Sources of the transistors M.sub.47 and M.sub.48 are connected to gates of the transistors M.sub.45 and M.sub.46, respectively. The above mentioned transistors constitute a second differential input summing circuit.
The second input voltage V.sub.2 is inverted by a differential circuit composed of transistors M.sub.59, M.sub.60, M.sub.61, M.sub.62 and M.sub.63 connected as shown. Outputs of this differential circuit are applied as a second input for the second differential input summing circuit.
Thus, the first differential input summing circuit receives the input voltages V.sub.1 and V.sub.2, and outputs (V.sub.1 +V.sub.2). On the other hand, the second differential input summing circuit receives the input voltages V.sub.1 and -V.sub.2, and outputs (V.sub.1 -V.sub.2).
These outputs of the first and second differential input summing circuits are supplied to a double differential squaring circuit composed of the transistors M.sub.39, M.sub.40, M.sub.49 and M.sub.50 and resistors R.sub.L11 and R.sub.L12.
An output V.sub.0 of this double differential squaring circuit is expressed by the following equation (37): ##EQU17## where (W/L).sub.1 is a ratio of a gate width to a gate length in the transistors M.sub.31 to M.sub.34 and M.sub.42 to M.sub.44 ;
(W/L).sub.2 is a ratio of a gate width to a gate length in the transistors M.sub.35 to M.sub.38 and M.sub.45 to M.sub.48 ; PA0 (W/L).sub.3 is a ratio of a gate width to a gate length in the transistors M.sub.39, M.sub.40, M.sub.49 and M.sub.50.
It will be seen from the equation (37) that a result of multiplication between the input voltages V.sub.1 and V.sub.2 can be obtained from the circuit shown in FIG. 2.
The above mentioned conventional multipliers have the following disadvantages:
The multiplier using the Gilbert circuit as shown in FIG. 1 is disadvantageous in that the linearity to the first input voltage V.sub.1 is not so good, as seen from the equation (33).
Turning to FIG. 3, there is shown a graph illustrating the result of simulation of the characteristics of the multiplier shown in FIG. 1. This simulation was made under a condition in which a processing condition is Tox=320 .ANG. (Tox is gate oxide thickness) and W/L=50 .mu.m/5 .mu.m. The result of simulation shows that the linearity can be obtained in a range of -0.2 V&lt;V.sub.1 &lt;0.2 V.
In the multiplier shown in FIG. 2, the differential input summing circuits are not so good in linearity, because of unbalance in circuit structure between the differential input summing circuits corresponding to the input voltages V.sub.1 and V.sub.2, respectively. In addition, a range of the double differential squaring circuit having a square-law characteristics is determined by a circuit structure, and is limited to an extent of -0.5 V&lt;V.sub.1, V.sub.2 &lt;0.5 V.